PLA, PAL , CPLD, FPGA

In the earlier 60's it was discrete logic used by electronic industry. The digital system would look like noodle like maze of wiring between components. Once it is built it will be difficult to do rework on it. Sometimes the designers would forget what they have designed for! Manufacturing such systems was very difficult and redesign will be so eye-shutting just like making a PCB every time we redesign. The chip manufactures resolved this issue by placing an unconnected array of AND-OR gates in a single chip device called a programmable logic device (PLD).

Reference: http://www.circuitstoday.com/understanding-fpga-and-cpld

ROM, PLA & PAL

The first PLD was ROM. ROM design was not very successful as it emerged the issue of hardware wastage and increasing exponential growth in the hardware for every large application. To overcome the limitations of ROM, PLA and PAL were devised.

PLA and PAL are types of Programmable Logic Devices (PLD) which are used to design combination logic together with sequential logic. The significant difference between the PLA and PAL is that the PLA consists of the programmable array of AND and OR gates while PAL has the programmable array of AND but a fixed array of OR gate.

BASIS FOR COMPARISON	PLA	PAL
Stands for	Programmable Logic Array	Programmable Array Logic
Construction	Programmable array of AND and OR gates.	Programmable array of AND gates and fixed array of OR gates.
Availability	Less prolific	More readily available
Flexibility	Provides more programming flexibility.	Offers less flexibility, but more likely used.
Cost	Expensive	Intermediate cost
Number of functions	Large number of functions can be implemented.	Provides the limited number of functions.
Speed	Slow	High

Definition of PLA

PLA stands for the Programmable Logic Array which presents the boolean function in the SOP (Sum of Products) form. The PLA contains NOT, AND and OR gates fabricated on the chip. It passes every input by a NOT gate which makes each input and its complement available to every AND gate. The output of each AND gate is given to the each OR gate. At last, the OR gate output produces chip output. So, this is how suitable connections are made to employ SOP expressions.

In PLA the connections to both AND and OR arrays are programmable. PLA is considered more expensive and complex as compared to the PAL. The two different manufacturing techniques can be used for PLA to increase the ease of programming. In this technique, each connection is built through a fuse at every intersection point where the unwanted connections can be removed by blowing the fuses. The latter technique involves the connection making at the time of the fabrication process with the help of the proper mask provided for the specific interconnection pattern.

Definition of PAL

PAL (Programmable Array Logic) is also a PLD (Programmable Logic Device) circuit which works similar to the PLA. PAL employs the programmable AND gates but fixed OR gates, unlike PLA. It implements two simple functions where the number of linked AND gates to each OR gate specifies the maximum number of product terms that can be generated in a sum-of-products representation of the particular function. While the AND gates are perpetually connected to the OR gates, which signifies that the produced product term is not shareable with the output functions.

The main concept behind developing PLD’s is to embed a complex boolean logic into a single chip. Therefore, eliminating the unreliable wiring, preventing the logic design and minimizing power consumption.

Reference: https://techdifferences.com/difference-between-pla-and-pal.html


A CPLD contains a bunch of PLD blocks whose inputs and outputs are connected together by a global interconnection matrix. So a CPLD has two levels of programmability: each PLD block can be programmed, and then the interconnections between the PLDs can be programmed.

An FPGA takes a different idea. It has a clump of simple, configurable logic blocks arranged in an array with interspersed switches that can rearrange the interconnections between the logic blocks. Each logic block is individually programmed to perform a logic function (such as AND, OR, XOR, etc.) and then the switches are programmed to connect the blocks so that the complete logic functions are implemented.

FPGA	CPLD
Suited for timing circuit because they have more registers.	CPLD is suited for control circuit because they have more combinational circuit.
Timing reports will be different if same code is synthesized many times.	Timing reports will be same result.
FPGA can be used to high-end product	CPLD can be used to low-end product
FPGA has more flexibility as well as design capacity.	CPLD has less compared to FPGA regarding design complexity
FPGA can operate at very high speed	CPLD has less
The FPGA are volatile in many cases, that’s way they need a configuration memory for working with programmed design.	CPLD devices are not volatile. They contain flash or erasable ROM memory in all of cases.
FPGA could not work untill the configuration is done.	The CPLD could work immediately after power up.
FPGA is RAM base.	CPLD is ROM base.
FPGAs are “fine-grain” devices. That means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops.	CPLDs are “coarse-grain” devices. They contain relatively few (a few 100’s max) large blocks of logic with flip-flops.
FPGAs have special routing resources to implement efficiently binary counters and arithmetic functions (adders, comparators…). CPLDs do not.	CPLDs have a faster input-to-output timings than FPGAs (because of their coarse-grain architecture, one block of logic can hold a big equation), so are better suited for microprocessor decoding logic for example than FPGAs.
FPGAs can contain very large digital designs	CPLDs can contain small designs only.